1. Field of the Invention
The present invention relates to a substrate potential detecting circuit in an integrated circuit (IC) with a complementary field effect transistor (FET) structure. More particularly, the present invention relates to a substrate potential detecting circuit used in an IC which may be manufactured by either a P-well process or an N-well process.
2. Description of the Related Art
In a layout design of the complementary semiconductor IC, it is a common practice that a layout pattern of the semiconductor device is designed so as to be adaptable for both a P-well structure and an N-well structure. In designing IC layout, a designer frequently handles two types of layout, one to be incorporated into a semiconductor layout only when the semiconductor layout is based on a P-well structure, and the other to be incorporated into a semiconductor layout only when it is based on an N-well structure. In this case, either one of the following two measures has generally been taken. In the first measure, both the layouts for the P-well and N-well, in design, are incorporated into a single semiconductor layout system. At the manufacturing stage, an Al (aluminum) wiring pattern is changed and/or modified to incorporate the intended type of the layout into the semiconductor layout. In the second measure, two different layouts for the respective well structures are designed.
The first measure employs an Al master slice method for changing and/or modifying the wiring pattern. In this method, the data of the Al wiring pattern necessary for the change and/or modification is prepared, then combined with the Al wiring pattern data common for both the P-well and N-well structures, thereby forming the desired Al wiring pattern data. The first measure, however, has the following two disadvantages. One is that a blank space must be reserved for the future use in the changing and/or modifying process of the Al wiring layer. The second is that two types of data, i.e., the data of the common Al wiring pattern and the data for the master slicing, must be prepared for obtaining a desired Al wiring pattern, and hence complicated data processing is required.
The second measure also has a disadvantage. This measure needs different layout designs respectively for the P-well structure and the N-well structure, so design work is doubled and consequently the possibility of error is increased.
FIG. 1 shows a transfer gate circuit when the Al master slice method is used. In the figure, P1 and P2, and N1 and N2 are open circuit points. When the transfer gate circuit of FIG. 1 is fabricated into a P-well structure and an N-well structure, those open circuit points become closed circuit points through the wiring layer based on the Al master slice method. The circuit points P1 and P2 are originally open, and when the semiconductor circuit is fabricated into the P-well structure, these are closed. The same thing is correspondingly applied for the circuit points N1 and N2. In FIG. 1, reference numeral 1 designates a transfer gate circuit; 2, a back-gate effect suppressing circuit; 3, a control circuit for transfer gate 1; 4, an input terminal; 5, an output terminal; 6, a control terminal; 7, an inverter; 8, a power source terminal; and 9, an interconnection wire made of, for example, aluminum.